1. Field of the Invention
The present invention relates to a semiconductor device and a method for controlling the semiconductor device. More particularly, the present invention relates to a semiconductor device capable of controlling the drain voltage in programming and a method for controlling the semiconductor device.
2. Description of the Related Art
FIG. 1 is a circuit diagram of a circuit involved in programming of a conventional non-volatile semiconductor memory device. A non-volatile semiconductor memory device 1 includes memory cells 21 and 22 and a program high-voltage supply circuit 3. The memory cells 21 and 22 are flash memory cells having a floating gate or a nitride film as a charge storage layer. In programming, a high voltage is applied to the selected cell, and a hot carrier is injected in the charge storage layer. A high voltage VPROG for programming used in the non-volatile semiconductor memory device 1 is generated by regulating a high voltage generated by a not-shown high-voltage generating circuit at a given constant level. The high programming voltage VPROG is applied to a common data bus line DATABn coupled to the bit lines via the program high-voltage supply circuit 3. The drain voltage of the cell to be programmed is supplied via the common data bus line DATABn where n indicates the width of the data bus line and ranges from, for example 0 to 15.
Generally, the voltage really applied to the drain of the memory cell to be programmed varies based on the state of the memory cell. More particularly, when the memory cell in the erased state is to be programmed, the gate of the memory cell is selected, so that the drain and source of the memory cell can conduct. The high programming voltage on the common data bus line is regulated at the given constant level, nevertheless the programming voltage drops at a position close to the memory cell. When the programming of the selected memory cell progresses, the threshold value of the cell is raised. Thus, even when the gate is in the selected state, the conduction between the drain and the source is weakened, and the voltage of the common data bus line is applied to the drain of the memory cell without dropping.
U.S. Pat. No. 5,422,842 discloses a device in which the programming current is compared with the reference current, and programming is terminated when the verification of programming passes.
Japanese Patent Application Publication 2001-15716 discloses a device that uses a constant-current element that limits the current applied to the drain of the memory cell to a given level.
The drain voltage for programming is required to be higher due to an increase in a drain resistance R of the memory cell caused by miniaturization in order to improve the capacity and rewriting speed of the non-volatile semiconductor memory device.
However, a drain disturb is likely to occur on the unselected memory cell 22 that shares the drain with the selected memory cell 21 because less current flows through the memory cell involved in programming at the end of programming or just prior to completion of programming and the drain voltage is thus raised. That is, as shown in FIG. 2, at the time of programming, when a signal PGMn becomes HIGH, the output of the high programming voltage drops due to the resistance because the cell is in the erased state. This causes a voltage slightly lower than the potential of the common data bus line DATABn to be applied to a metal bit line M1BL. Then, less current flows through the memory cell 21 as the programming progresses, and the voltage of the metal bit line M1BL reaches the level of the common data bus line DATABn. When the voltage of the metal bit line M1BL is high, a drain disturb may occur on the unselected memory cell 22 that shares the drain with the selected memory cell 21.
The proposal disclosed in U.S. Pat. No. 5,422,842 does not solve the above problem. The proposal in Japanese Patent Application Publication 2001-15716 does not solve the above problem.